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6.4T+ Optical Engine for CPO

TOE-400G Tx Optical Engine

Higher level of integration is achieved through visionary products, integrating as many lanes as the application requires. Plasmonic modulators enable applications with 8, 16 and 32 lanes, providing industry’s leading channel density for demanding applications. Optimized driver integration enhances RF performance through refined signal paths and lower drive voltages.

Key Features

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    145 GHz EO Bandwidth

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    0.5 pJ/bit (driver and EOM)

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    Optical output power up to 4 dBm
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    Bit error rate better than 1E-6

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6.4T+ CPO

Description

The TOE-400G transmit engine for co-packaged optics (CPO) delivers industry-leading integration and ultra-high channel density with support for 16 and 32 lanes, making it ideal for next-generation data center and AI workloads.

With tightly integrated drivers and modulators, the system is optimized for minimal signal path length, enhanced RF performance, and reduced drive voltages—enabling both a smaller form factor and superior signal fidelity. Its cutting-edge architecture achieves energy efficiency below 0.5 pJ/bit by eliminating static currents and electrode bias, relying instead on a purely capacitive load with a clear roadmap for further reductions.

Designed for uncompromising reliability, the engine achieves a bit error rate as low as 1E-6, delivering excellent signal integrity and clean eye diagrams for high-performance optical interconnects.

Leader in Power Reduction

Plasmonic lumped devices have optimized RF characteristics that make the driver consume less switching power. It’s actually a benefit that comes with the unprecedented speed of plasmonic circuits. In a first step we are pushing below 0.5 pJ/bit (including DRV and EOM power dissipation). Then we will half this again every year thanks to architecture improvements.

Differentiating by Signal Integrity

Driver integration and control of the RF properties of the CPO component provides a game changer for the industry. The result is cleaner RF signal propagation and better transfer to the optical domain, better eye diagrams and lower bit error rate (BER).

Form Factor Advantage

The application benefits either from more lanes per area, smaller optical engines, and higher data throughput. The power density is not increased, since plasmonic circuits consume overall less power than alternatives.

CMOS Compatibility

Simplifies integration with existing semiconductor manufacturing processes, reducing production costs, enhancing scalability, and enabling integration of logic and the optical engine.

Performance Specifications

3.2T6.4T12.8T
Peak wavelength1310 nm1310 nm1310 nm
Number of lanes81632
Power dissipation (driver+EOM+ control electronics)0.5 pJ/bit = 1.6 W (8 lanes)0.5 pJ/bit = 3.2 W (16 lanes)0.5 pJ/bit = 6.4 W (32 lanes)
Optical input power per lane13 dBm13 dBm13 dBm
Optical output power per lane (AOP)-0.9 ... 4 dBm-0.9 ... 4 dBm-0.9 ... 4 dBm
Optical modulation amplitude (OMA)1.2 ... 4.2 dBm1.2 ... 4.2 dBm1.2 ... 4.2 dBm
Dynamic extinction ratio (dER)>4 dB>4 dB>4 dB
TDECQ<3.4 dB<3.4 dB<3.4 dB
Bit error rate (BER)<1E-6<1E-6<1E-6